Previous Project
 |
Channel Modeling and Readback Signal Simulation Modeling of the magnetic recording channel is an ongoing project at the CDSLab. An important tradeoff exists between the complexity of the simulator and its accuracy. While a model based on micromagnetics may provide extremely precise results, such a technique is too slow for monte carlo simulation of data recovery circuits. Instead, the a linear channel model with first order nonlinear effects such as transition broadening, bit shift, and partial erasure is used. Although less precise than a micromagnetic model, the results from this type of simulator can be used to accurately evaluate various types of signal processing. Additional details can be found in
Intensive simulation is often carried out to investigate advanced signal processing techniques for data storage applications. The simulation is normally performed in software that may take a very long time. For instance, a simulation of BER=10^(-8) with 10 errors that runs on a personal computer equipped with a 1GHz Pentium 4 processor can take days. On the other hand, target BERs in commercial hard drives normally go below 10 out of 10^(13) for desktop products and 10 out of 10^(15) for server-class products. One approach to speed up the simulation process is to implement the whole simulator or part of it into hardware. Because the noise characteristics in hard-drives are unique, the assumption of additive white Gaussian noise (AWGN) is not sufficient. Instead, a dedicated readback signal generator must be implemented in front of data-recovery modules in the simulator. This signal generator shall incorporate all major noise processes and distortions and is capable of generating very low probability events according to the user-defined statistics. It shall also have the reconfiguration capability that allows the user to choose from various noise and distortion combinations. Field programmable gate array (FPGA) becomes the choice of implementation platform because of its advantage on low-cost and reconfigurability. The FPGAbased signal generator can also serve as a test bench for data-recovery circuit (usually called the "read channel") since it is totally tunable compared to typical test spindle setups and it can provide a complete set of test conditions. A readback signal generator has been implemented in a Xilinx Virtex?E FPGA device. Noise processes and distortions observed in hard drives have been modeled and simulated in hardware. Embedded non-uniform random number generators can provide accurate randomness. The signal generator is capable of simulating readback pulses, intersymbol interference, transition noise, electronics noise, head and media nonlinearity, intertrack interference, and write timing error according to the characteristics specified by the user. A sample implementation is demonstrated at 70 MHz clock speed. The runtime of generating 10^(12) pulses on an FPGA-based generator is 4 hours compared to about 10000 hours in software. Scaling of the design is handy to perform when aiming at different error rates. Additionally, the generator provides the user with flexibility and helps increase the capacity of the FPGA device through real-time reconfiguration. The proposed readback signal generator can be integrated into a FPGA read channel simulator or serve as a test bench for a data-recovery circuit. For more information, see
|
|
Copyright @ University of Minnesota CDSLab |